-------------------------------------------------------- | | | NanoSim Version G-2012.06 (RHEL64) | | Copyright (c) 2012 Synopsys Inc., All Rights Reserved. | | | -------------------------------------------------------- Built by nsmgr on Fri May 18 18:17:12 PDT 2012 Mon Jun 24 12:15:47 EDT 2013 Machine Name: parsnip Command line options: -n modulo12_hw_0_hd_0_hwVal_0_hdVal_0-gate_K0_I1000.sp -o modulo12_hw_0_hd_0_hwVal_0_hdVal_0-gate_K0_I1000 -c modulo12_hw_0_hd_0_hwVal_0_hdVal_0-gate_K0_I1000.cfg The 64-bit version of the simulator is running. Initializing system messages took 0.010 s LICENSE Information: -- Key: TIMEMILL__NSADDON -- Version: 2012.06 Installing interactive/configuration commands ... Installing commands took 0.000 s Start netlist compilation at Mon Jun 24 12:15:48 2013 Compiling "modulo12_hw_0_hd_0_hwVal_0_hdVal_0-gate_K0_I1000.sp" (SPICE) Compiling "/home/borowcm/libraries/saed90nm.cdl" (SPICE) Compiling "/home/borowcm/libraries/SAED90nm.lib" (SPICE) Compiling "/home/borowcm/libraries/SAED90nm.lib" (SPICE) Compiling "modulo12_hw_0_hd_0_hwVal_0_hdVal_0-gate_K0_I1000_stim.sp" (SPICE) Parsing netlist finished in 0 seconds Default circuit temperature : 25.000 Netlist compilation will be case insensitive. All letters will be converted to lower case. Building instance tree finished in 0 seconds Finish netlist compilation at Mon Jun 24 12:15:48 2013 Netlist compilation took 0.090 s NOTICE:Techfile Voltage (*nanosim tech="voltage") set to 1.2V ... This simulation uses HSPICE models WARNING:NanoSim:0x21104432:MISC MODEL PROBLEM: ** warning** associated with encrypted blocks were suppressed Building node/element arrays took 0.070 s Reading configuration files ... Reading configuration files took 0.000000 s WARNING:NanoSim:0x21108427:Output current waveform sampling resolution (= 1e-15 A) is smaller than the simulation current resolution (= 1e-12 A). WARNING:NanoSim:0x2110925a:There are 0 DANGLING nodes and 3 DANGLING STIMULUS SIGNALS. Please view the file modulo12_hw_0_hd_0_hwVal_0_hdVal_0-gate_K0_I1000.dng for the node names # of CMOS elements : 2 # of resistors : 1 # of dc voltage sources : 2 # of independent sources : 3 # of current controlled current sources : 1 # of elements : 9 # of used elements : 8 # of nodes : 9 # of subckt : 342 # of top-level instances : 8 # of capacitors from netlist : 1 # of Ground CAPS from netlist : 1 # of Coupling CAPS from netlist : 0 Circuit partitioning ... Among 1 stages, there are: 0 pwl stages 0 grouped pwl stages 1 analog stages 0 NR stages 0 grouped analog stages 0 rc stages 0 ud stages 0 ADFMI functional model stages 3 nodes in the largest pwl stage 0 nodes in the largest digital stage 1 stages (1 pwl/analog stages) with 0-9 nodes Among 9 nodes, there are: 0 pwl nodes 3 analog (accurate) nodes 6 rc nodes 0 ud nodes 0 cut nodes 0 mem_cut nodes 3 no_clamp nodes 3 nodes in stages 6 voltage source nodes 3 constant nodes 0 NR nodes Among 9 elements, there are: 5 elements in stages 5 pwl elements 0 synchronous elements 0 SMS elements 0 analog (accurate) elements 0 rc elements 0 ud elements 0 ADFMI functional model elements 0 VERILOGA model elements 0 behavioral model elements 5 mna elements 0 NR elements 0 mos transistors identified as keepers 2 mos transistors need Subthreshold current 0 keepers removed 0 keepers reduced Circuit partitioning took 0.000 s Constructing matrix ... Matrix ordering and construction took 0.000 s After reading configuration file(s), 1 signals are identified to be printed: 1 element branch current signals, including: 1 element branch inst. current signals Statistics of memory used for signal printing: 424120 bytes allocated in total, including: 160000 bytes allocated additionally for node current signals 264120 bytes allocated additionally for element branch current signals Levelizing stages ... Levelizing stages took 0.000 s DC initialization ... Finishing initialization (level 0 -- 0) 0 dynamic stages assigned in DC Initialization Number of residual dc events scheduled : 0 Number of ic nodes scheduled : 0 DC initialization took 0.000 s Simulation begins in pwl mode ... Simulation ends at 10040.000 ns Simulation took 0.010 s Current information calculated over the intervals: 0.00000e+00 - 1.00400e+04 ns Simulation time resolution : 1.000e-02 ns Print time resolution : 1.000e-02 ns Number of PWL matrix solutions : 12 Number of PWL MOS model lookups : 26 Number of time steps : 0 Number of iterations : 0 Number of rejected time steps : 0 Global simulation parameters used: SPD 0.18V ASPD 0.06V SIM_DESV 0.18V SIM_AESV 0.06V VDS_MIN 2.37675e-10V AVDS_MIN 2.37675e-10V SSC (steady state current) 1e-07uA SUBI (subthreshold current) 1e-06uA DC CURRENT 1e-06uA 2.0 real 0.6 user 0.1 sys Signal data is saved in modulo12_hw_0_hd_0_hwVal_0_hdVal_0-gate_K0_I1000.out No errors reported in the .err file (modulo12_hw_0_hd_0_hwVal_0_hdVal_0-gate_K0_I1000.err)