-------------------------------------------------------- | | | NanoSim Version G-2012.06 (RHEL64) | | Copyright (c) 2012 Synopsys Inc., All Rights Reserved. | | | -------------------------------------------------------- Built by nsmgr on Fri May 18 18:17:12 PDT 2012 Mon Nov 12 21:56:40 EST 2012 Machine Name: linux-test-64bit Command line options: -n binaryFSM_K0_I50.sp -o binaryFSM_K0_I50 -c binaryFSM_K0_I50.cfg The 64-bit version of the simulator is running. Initializing system messages took 0.000 s LICENSE Information: -- Key: TIMEMILL__NSADDON -- Version: 2012.06 Installing interactive/configuration commands ... Installing commands took 0.010 s Start netlist compilation at Mon Nov 12 21:56:41 2012 Compiling "binaryFSM_K0_I50.sp" (SPICE) Compiling "/home/borowcm/libraries/saed90nm.cdl" (SPICE) Compiling "/home/borowcm/libraries/SAED90nm.lib" (SPICE) Compiling "/home/borowcm/libraries/SAED90nm.lib" (SPICE) Compiling "binaryFSM_K0_I50_stim.sp" (SPICE) Parsing netlist finished in 0 seconds Default circuit temperature : 25.000 Netlist compilation will be case insensitive. All letters will be converted to lower case. Building instance tree finished in 0 seconds Finish netlist compilation at Mon Nov 12 21:56:41 2012 Netlist compilation took 0.100 s NOTICE:Techfile Voltage (*nanosim tech="voltage") set to 1.2V ... This simulation uses HSPICE models WARNING:NanoSim:0x21104432:MISC MODEL PROBLEM: ** warning** associated with encrypted blocks were suppressed Building node/element arrays took 3.790 s Reading configuration files ... Reading configuration files took 0.000000 s WARNING:NanoSim:0x21108427:Output current waveform sampling resolution (= 1e-15 A) is smaller than the simulation current resolution (= 1e-12 A). # of CMOS elements : 248 # of resistors : 1 # of dc voltage sources : 2 # of independent sources : 3 # of current controlled current sources : 1 # of elements : 255 # of used elements : 254 # of nodes : 128 # of subckt : 342 # of top-level instances : 34 # of capacitors from netlist : 1 # of Ground CAPS from netlist : 1 # of Coupling CAPS from netlist : 0 Circuit partitioning ... Among 1 stages, there are: 0 pwl stages 0 grouped pwl stages 1 analog stages 0 NR stages 0 grouped analog stages 0 rc stages 0 ud stages 0 ADFMI functional model stages 122 nodes in the largest pwl stage 0 nodes in the largest digital stage 1 stages (1 pwl/analog stages) with 100-149 nodes Among 128 nodes, there are: 6 pwl nodes 122 analog (accurate) nodes 0 rc nodes 0 ud nodes 0 cut nodes 0 mem_cut nodes 128 no_clamp nodes 122 nodes in stages 6 voltage source nodes 3 constant nodes 0 NR nodes Among 255 elements, there are: 251 elements in stages 3 pwl elements 16 pwl+ elements 0 synchronous elements 0 SMS elements 232 analog (accurate) elements 0 rc elements 0 ud elements 0 ADFMI functional model elements 0 VERILOGA model elements 0 behavioral model elements 251 mna elements 0 NR elements 0 mos transistors identified as keepers 248 mos transistors need Subthreshold current 0 keepers removed 0 keepers reduced Circuit partitioning took 0.000 s Constructing matrix ... Matrix ordering and construction took 0.000 s After reading configuration file(s), 1 signals are identified to be printed: 1 element branch current signals, including: 1 element branch inst. current signals Statistics of memory used for signal printing: 426088 bytes allocated in total, including: 160000 bytes allocated additionally for node current signals 266088 bytes allocated additionally for element branch current signals Levelizing stages ... Levelizing stages took 0.000 s DC initialization ... WARNING:NanoSim:0x2110e526:Element xu25.mmp4 outside tech_file range (vg=0.91173, vd=0.056927, vs=1.6)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu25.mmp3 outside tech_file range (vg=-0.436138, vd=1.2, vs=1.6)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu27.mmp2 outside tech_file range (vg=-0.199415, vd=1.2, vs=1.6)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu27.mmp1 outside tech_file range (vg=-0.436138, vd=1.2, vs=1.6)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu23.mmn1 outside tech_file range (vg=1.30127, vd=0, vs=-0.548915)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu23.mmp1 outside tech_file range (vg=1.30127, vd=-0.548915, vs=1.2)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu29.mmp1 outside tech_file range (vg=-0.199415, vd=1.2, vs=1.6)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu19.mmp2 outside tech_file range (vg=-0.436138, vd=1.2, vs=1.6)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu30.mmp1 outside tech_file range (vg=-0.436138, vd=1.2, vs=1.6)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu26.mmp1 outside tech_file range (vg=-0.436138, vd=1.2, vs=1.6)... at 0ns WARNING:NanoSim:0x20102001:Previous message has been printed 10 times, It will not be printed again! To change the limit for every message type, use: "set_mesg_opt limit_per_mesg=" WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x20102001:Previous message has been printed 10 times, It will not be printed again! To change the limit for every message type, use: "set_mesg_opt limit_per_mesg=" Finishing initialization (level 0 -- 0) 0 dynamic stages assigned in DC Initialization Number of residual dc events scheduled : 0 Number of ic nodes scheduled : 0 DC initialization took 0.010 s Simulation begins in pwl mode ... WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xstate_reg[1].mmn4, vbs=0.419969... at 25ns WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xstate_reg[1].mmn6, vbs=0.419969... at 25ns WARNING:NanoSim:0x2110f526:Element xstate_reg[1].mmn6 outside tech_file range (vg=0.211737, vd=1.23689, vs=-0.419969)... at 25ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f526:Element xu26.mmn1 outside tech_file range (vg=-0.00522597, vd=1.2188, vs=-0.365568)... at 25.03ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f526:Element xstate_reg[0].mmp11 outside tech_file range (vg=1.20563, vd=-0.0196392, vs=1.49126)... at 30ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f526:Element xstate_reg[0].mmp12 outside tech_file range (vg=1.20453, vd=-0.0196392, vs=1.49126)... at 30ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f526:Element xstate_reg[1].mmp11 outside tech_file range (vg=1.20563, vd=-0.01164, vs=1.47252)... at 30ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f526:Element xstate_reg[1].mmp12 outside tech_file range (vg=1.20448, vd=-0.01164, vs=1.47252)... at 30ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f526:Element xnextstate_reg[2].mmn9 outside tech_file range (vg=0.263334, vd=1.50584, vs=0)... at 30.06ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f526:Element xnextstate_reg[1].mmp7 outside tech_file range (vg=0.789905, vd=-0.312101, vs=1.19996)... at 30.09ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f525:Negative bulk-source bias: element xstate_reg[2].mmp10, vbs=-0.433412... at 40ns WARNING:NanoSim:0x2110f525:Negative bulk-source bias: element xstate_reg[2].mmp12, vbs=-0.433412... at 40ns WARNING:NanoSim:0x2110f526:Element xstate_reg[2].mmp12 outside tech_file range (vg=1.21066, vd=-0.00795287, vs=1.63338)... at 40ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xstate_reg[0].mmn4, vbs=0.420531... at 45ns WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xstate_reg[0].mmn6, vbs=0.420531... at 45ns WARNING:NanoSim:0x2110f526:Element xstate_reg[0].mmn6 outside tech_file range (vg=0.212006, vd=1.23694, vs=-0.420531)... at 45ns WARNING:NanoSim:0x20102001:Previous message has been printed 10 times, It will not be printed again! To change the limit for every message type, use: "set_mesg_opt limit_per_mesg=" WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x20102001:Previous message has been printed 10 times, It will not be printed again! To change the limit for every message type, use: "set_mesg_opt limit_per_mesg=" WARNING:NanoSim:0x2110f525:Negative bulk-source bias: element xu36.mmp4, vbs=-0.439814... at 49.98ns WARNING:NanoSim:0x2110f525:Negative bulk-source bias: element xu36.mmp3, vbs=-0.439814... at 49.98ns WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xu30.mmn2, vbs=0.723035... at 75.03ns WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xu30.mmn1, vbs=0.723035... at 75.03ns WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xu27.mmn2, vbs=0.471936... at 85.09ns WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xu27.mmn1, vbs=0.471936... at 85.09ns WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xstate_reg[0].mmn03, vbs=0.430001... at 85.18ns WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xstate_reg[0].mmn1, vbs=0.430001... at 85.18ns WARNING:NanoSim:0x20102001:Previous message has been printed 10 times, It will not be printed again! To change the limit for every message type, use: "set_mesg_opt limit_per_mesg=" Simulation ends at 540.000 ns Simulation took 1.240 s Current information calculated over the intervals: 0.00000e+00 - 5.40010e+02 ns Simulation time resolution : 1.000e-02 ns Print time resolution : 1.000e-02 ns Number of PWL matrix solutions : 5738 Number of PWL MOS model lookups : 1370044 Number of time steps : 5676 Number of iterations : 0 Number of rejected time steps : 1792 Global simulation parameters used: SPD 0.06V ASPD 0.024V SIM_DESV 0.06V SIM_AESV 0.024V VDS_MIN 9.34266e-11V AVDS_MIN 9.34266e-11V SSC (steady state current) 1e-07uA SUBI (subthreshold current) 1e-06uA DC CURRENT 1e-06uA 6.0 real 5.6 user 0.1 sys Signal data is saved in binaryFSM_K0_I50.out No errors reported in the .err file (binaryFSM_K0_I50.err)